(1) Field of the Invention
The present invention concerns a device isolation structure in a semiconductor device including MOS transistors, a manufacturing method thereof and an application method thereof.
(2) Description of the Prior Art
As a device isolation technique in semiconductor devices, a method of filling the inside of a shallow groove opened in the surface of a substrate with an insulation material has been known. Typical literatures disclosing the related art are shown below.
(1) Literatures described in xe2x80x9cI. Triple Ease, 1994, International Electron Device Meeting, Technical Digestxe2x80x9d, p675-p678, (2) literatures described in xe2x80x9cI. Triple Ease, 1996, International Electron Device Meeting, Technical Digestxe2x80x9d, p829-p832, (3) Japanese Published Unexamined Patent Application No. Sho 61-214446, (4) Japanese Published Unexamined Patent Application No. Hei 2-260660, (5) Japanese Published Unexamined Patent Application No. Hei 6-204333 and (6) Japanese Published Unexamined Patent Application No. Hei 9-181163.
The known literature (1) describes use of a shallow device isolation structure together with a device isolation structure by selective thermal oxidation (LOCOS). This is said to be an effective technique for preventing excess polishing which causes problem in chemical mechanical polishing method (hereinafter referred to as CMP). However, since the surface step is similar with that in the existent LOCOS, it can not cope with a narrow lithographic focus latitude upon conducting refined side fabrication.
Accordingly, the known technique (1) does not always meet refinement and high integration degree of semiconductor devices.
The technique disclosed in the known reference (2) forms a thermal oxide film of 50 nm to 100 nm in a device isolation area and then shallow groove is opened by disposing a spacer made of an insulator on the side wall of a mask layer used upon thermal oxidation. In this technique, since the spacer remains upon filling the inside of the groove, the aspect ratio (depth to width) of the groove increases. Therefore, it is difficult to fill the inside of the groove, which hinders refinement. For improving the integration degree in a semiconductor memory or improving the performance of a microprocessor by forming a fine MOS transistor, it is very much important to form a fine shallow groove isolation structure.
Sharpening of a substrate at the surface edge of the shallow groove isolation structure and localized decreasing in the thickness of the gate oxide film become more remarkable as the thickness of the gate oxide film is increased. That is, as the film thickness increases, a tunnel current through the gate oxide film flows at a lower electric field.
FIG. 46 shows a relation between an electric field applied to the gate oxide film and a tunnel current flowing through the oxide film. A specimen used for the measurement is a rectangular MOS capacitor surrounded at four sides with a shallow groove isolation area formed by the prior art. The thickness of the thermal oxide shown in the drawing is that for a flat portion. As shown in FIG. 46, as the thickness of the thermal oxide film is larger, a tunnel current flows from a lower electric field and a dielectric break down voltage is also lowered. This is caused by the decrease in the thickness of the gate oxide film and sharpening of the substrate occurring at the surface edge of the shallow groove. This causes degradation of the gate withstand voltage of MOS transistors.
Since a semiconductor nonvolatile memory treats a high voltage at the inside, a MOS transistor having thick gate oxide film is necessary. Further, also in a microprocessor operating at a low internal voltage, since I/O section requires a circuit for treating a high voltage, it requires an MOS transistor having a thick gate oxide film. The situation is identical also in a semiconductor device in which a DRAM memory and a microprocessor are formed on one identical substrate, so long as I/O is concerned.
Existent shallow groove isolation structures are suitable to MOS transistors having thin gate oxide film, but the foregoing undesired phenomenon becomes conspicuous as the thickness of the gate oxide film increases. Accordingly, it is impossible to conduct desired operation of semiconductor devices by the use of the prior art to the semiconductor devices. None of the known literatures discloses the technique capable of overcoming the problems. Then, it is extremely important to solve the problems.
As a means for solving the foregoing problems, in an MOS structure having gate oxide films at a plurality of levels for the thickness on one identical substrate (for example, silicon substrate), a relation: Rxe2x89xa7r is defined providing that Hxe2x89xa7h between a radius of curvature R at a surface edge of a groove isolation structure on the side of a substrate in contact with a gate insulation film of a thickness H and a radius of curvature r at a surface edge of a groove isolation structure on the side of the substrate in contact with a gate oxide film of a thickness h. The relation can be considered as shown in FIG. 1. The radius of curvature for the corner at the surface edge of a shallow groove isolation on the side of the substrate where shallow groove isolation area disposed on SUB11 and a gate dielectric HOX1 are in contact with each other is assumed as R. GROXI11 is a silicon oxide film for device isolation filled in the shallow groove. POLY11 is a gate electrode present just thereon. A radius of curvature for the corner at the surface edge of a shallow groove isolation area on the side of the substrate where shallow groove isolation disposed on SUB11 and a gate oxide film LOX1 are in contact with each other is assumed as r. GROXI12 is a silicon oxide film for device isolation filled in the shallow groove. POLY12 is a gate electrode present just thereon. The feature of the present invention resides in establishing a relation: Rxe2x89xa7r, providing that HOX1xe2x89xa7LOX1.
As another means for dissolving the dissolving problems, a relation Hxe2x89xa7h is defined in an MOS structure having gate oxide films at a plurality of levels for thickness on one identical substrate, in which T is a step between the top of the side wall plane of the shallow groove in contact with a gate oxide film of a thickness H and the bottom of a gate oxide film of a thickness H, and it is a step between the top of the side wall plane of the shallow groove in contact with a gate oxide film of a thickness L and the bottom of a gate oxide film of a thickness L, providing that Hxe2x89xa7h.
The meaning is to be explained with reference to FIG. 2. T is a difference of height between the top of the shallow groove side wall and the bottom of the gate oxide film at the surface edge of shallow groove isolation where the shallow groove isolation area disposed on SUB21 and the gate dielectric HOX2 are in contact with each other. GROXI21 is an oxide film for device isolation filled in the shallow groove. POLY21 is a gate electrode present just thereon. t is a difference of height between the top of the shallow groove side wall and the bottom of the gate oxide film at the surface edge of shallow groove isolation where the shallow groove isolation area disposed on SUB12 and the gate dielectric LOX2 are in contact with each other. GROXI22 is an oxide film for device isolation filled in the shallow groove. POLY22 is a gate electrode present just thereon. The feature of the present invention resides in establishing the relation Txe2x89xa7t, providing that HOX1xe2x89xa7LOX1.
As a further means for dissolving the foregoing problems, a relation: Dxe2x89xa7d is defined in an MOS structure having gate oxide films at a plurality of levels for thickness on one identical substrate, in which D is a length along an inclined surface continuous from a horizontal bottom of a gate oxide film of a thickness H toward the top of the steepest side wall plane the shallow groove in contact with the gate oxide film of a thickness H, and d is a length along an inclined surface continuous from a horizontal bottom of a gate oxide film of a thickness L toward the top of the side wall plane of the shallow groove in contact with the gate oxide film of a thickness L, providing that Hxe2x89xa7L.
In this case, the substrate can be a silicon substrate and the oxide film can be a silicon oxide film.
The meaning is to be explained with reference to FIG. 3. D is a length of an area where the bottom of the gate oxide film is inclined toward the top of the steepest side wall plane of the shallow groove at the surface edge of the shallow groove isolation where the shallow groove isolation area disposed on SUB31 and the gate dielectric HOX3 are in contact with each other. GROXI31 is a silicon oxide film for device isolation filled in the shallow groove. POLY31 is a gate electrode present just thereon. d is a length of an area where the bottom of the gate oxide film is inclined toward the top of the steepest side wall plane of the shallow groove at the surface edge of the shallow groove isolation where the shallow groove isolation area disposed on SUB32 and the gate dielectric LOX3 are in contact with each other. GROXI32 is a silicon oxide film for device isolation in the shallow groove. POLY32 is a gate electrode present just thereon. The feature of the present invention resides in establishing the relation: Dxe2x89xa7d, providing that HOX1xe2x89xa7LOX1.
The concept of the present invention is to make the structure of the surface edge of the shallow groove isolation different corresponding to the thickness of the gate oxide film. This concept is applicable also to a case in which the gate dielectric is formed by chemical vapor deposition.
If the gate dielectric is formed by chemical vapor deposition, localized decrease in the thickness of the gate oxide film as caused by the thermal oxidation step can be avoided. However, the shape for the surface edge of the shallow groove isolation is still sharp if it is merely formed by the process, and the situation is identical in that the radius of curvature on the side of the substrate has to be set corresponding to the concentration of the electric field. Accordingly, also in the use of the gate dielectric formed by chemical vapor deposition, the present invention is also effective and necessary. Such a structure is important in an area forming the MOS structure as disclosed in FIG. 1 to FIG. 3. That is, the present invention is important for such a structure where the gate electrode is present at the surface edge of the shallow groove isolation and a gate electrode is present just thereon.
A manufacturing means for realizing the present invention comprises:
a step of depositing a thermal oxide mask layer on a silicon substrate,
a step of exposing a substrate in an area forming a device isolation structure,
a step of thermally oxidizing the exposed surface of the silicon substrate thereby providing a bird""s beak to the surface edge of a device isolation area,
a step of forming a spacer made of a material to be removed simultaneously with etching for the substrate to the side wall of the thermal oxide mask layer,
a step of anisotropically fabricating the thermal oxide film on the surface of the substrate using the thermal oxide mask layer and the spacer as a mask,
a step of anisotropically fabricating the exposed silicon substrate thereby forming a shallow groove,
a step of completely filling the inside of the shallow groove with an insulation material,
a step of retracting the field material thereby exposing the above-mentioned thermal oxide mask layer,
a step of removing the thermal oxidation mask layer thereby exposing a silicon substrate,
a step of forming a first gate insulation film on the exposed substrate,
a step of removing a first gate insulation material on a portion of an area thereby exposing the silicon substrate again,
a step of forming a second gate insulation film to the exposed surface of the substrate, and
a step of forming a gate electrode.
The thickness of the first gate dielectric is greater than that of the second gate dielectric.
The feature of the present invention regarding the shallow groove isolation and the manufacturing method thereof resides in that (A) it is not used together with a device isolation method only for LOCOS, (B) the material of the spacer disposed to the side wall of the mask for aperturing the shallow groove is identical with that for the substrate, or such a material as removed simultaneously upon etching of the substrate, that is, the spacer does not remain upon filling of the shallow groove. The manufacturing method and the structure described above are applied irrespective of the width, length and area of the shallow groove device isolation area.
A further feature in view of the structure according to the present invention resides in an angle at which the side wall of the shallow groove and the surface of the substrate intersect to each other. This becomes conspicuous in the relation between the thickness of the spacer disposed on the side wall of the thermal oxide mask layer and the thermal oxide film for forming the bird""s beak at the surface edge.
Problems are shown with reference to FIG. 4a to FIG. 4d and the manufacturing method according to the present invention for overcoming them are shown with reference to FIG. 5a to FIG. 5d. As shown in FIG. 4a, a spacer PSW4 is disposed on the side wall of a thermal oxide mask layer LSIN4 on a thermal oxide film TOX4. The film thickness tSWA of PSW4 is set such that the bottom edge of PSW4 on the side not in contact with LSIN4 is present just on an area where the bottom of the thermal oxide film BOX4 becomes horizontal. BOX4 is cut using PSW4 as a mask to form BBOX4 (FIG. 4b), and when a shallow groove is formed successively, ∠A is approximate to a right angle (FIG. 4c). In such a shape, when the polishing by CMP for the silicon oxide film GROX14 filling the shallow groove is excessive to expose the point A, the substrate is inevitably sharpened upon forming the gate oxide film GODX4 (FIG. 4d). On the other hand, in FIG. 5a, the thickness tSWB of PSW5 is set such that the base edge of the spacer PSW5 on the side not in contact with the thermal oxide mask layer LSIN5 is present just on an area where the bottom of the thermal oxide film BOX5 is inclined. BOX5 is cut at a bird""s beak area thereof using LSIN5 and PSW5 just above the thermal oxide film TOX5 as a mask to form BBOX5 (FIG. 5b). When a shallow groove is formed successively, an angle ∠B formed between the inner wall of the shallow groove and the bottom of BBOX5 becomes blunt (FIG. 5c). In this state, even if the point B is exposed by excess polishing by CMP, sharpening of the substrate can be suppressed upon forming the gate oxide film TOX5 (FIG. 5d). It is necessary to provide a shape for making ∠B blunt in order to prevent sharpening at the surface edge of the shallow groove isolation. In the foregoings, a manufacturing method including the formation of the spacer has been explained specifically, but the spacer can be saved so long as the shape of the present invention can be attained finally.
The manufacturing method explained in this chapter is an example for practicing the present invention. It should be understood that the conceptional feature of the present invention is in a relation between the film thickness of the gate dielectric just below the gate electrode and the shape of the surface edge of shallow groove isolation in contact therewith. As has been explained at the last of the preceding chapter, the semiconductor device for which the present invention is most important is, for example, a nonvolatile memory in which gate oxide films are present at a plurality of levels for thickness, a microprocessor, a semiconductor device in which they are formed on one identical substrate and a semiconductor device in which a DRAM memory and a microprocessor are formed on one identical substrate.
Further, although the manufacturing method explained in this chapter is suitable to embody the shallow groove isolation according to the present invention, it is applied and effective also in a case where the gate oxide film is at a single level of thickness. This is because the problem of excess polishing by CMP has to be solved also in a case where the gate oxide is at a single level of thickness.